In electronic systems, good clock distribution is very important to the overall performance of the electronic systems in general. Unwanted clock skew and jitter typically result from poor clock distribution and cause problems in the design and operation of the electronic systems. Techniques have been developed using PLLs to mitigate the effect of these problems to manageable levels. Therefore, PLLs are widely used in electronic circuits.
When PLLs are implemented in integrated circuits (IC), variations in behavior may occur due to device mismatch, offset, and/or leakage. These undesirable variations may affect the static phase error (SPE) of signals sampled by the output clock signals of the PLLs. The SPE is defined as the deviation from the crossing of a sampling clock to the center of an eye diagram of the signals sampled. FIG. 1A shows a sample eye diagram for a signal sampled by an existing PLL.
FIG. 1B shows one conventional PLL. The PLL 100 includes a number of fixed path delay elements 110 inserted into the signal paths between a sampling clock and input data to tune or to adjust the SPE. By adjusting the setup and hold time of the sampling flip-flop 120, the bit error rate can be reduced. Typically, the fixed path delays 100 are built with resistive and capacitive (RC) components, buffers, and/or metal lines.
However, the conventional PLL suffers from a number of disadvantages. One disadvantage of the conventional technology is the extra deterministic jitter, also known as inter symbol interference (ISI). The ISI may be generated as the fixed path delays are used to tune the SPE. Furthermore, since various offsets and mismatches in the conventional PLL might be random, having one fixed delay setting as provided by the fixed delay elements 110 in FIG. 1B may not provide satisfactory SPE compensation across process variation, voltage, and temperature (PVT). Without a satisfactory SPE compensation across PVT, the production yield of PLLs falls. Having a satisfactory production yield is important in making a semiconductor product successful because it is typically uneconomical to manufacture a low yield product. An improvement in yield usually corresponds to an increase in profit. Furthermore, the cost of an IC is typically a function of the die size, wafer cost, technology, and yield (i.e., number of good dies per wafer). The issue of yield improvement is especially critical in highly integrated products with high die area, in which PLLs are widely used.